OpenAI and Broadcom Unveil 'Jalapeño' — OpenAI's First Custom AI Inference Chip

700W peak, ~550W sustained power draw per chip

The Jalapeño chip is rated at 700W peak, with measured sustained draw closer to 550W under production inference workloads — a key power-efficiency datapoint for datacenter planning.

Full system: 2,048 accelerators, 27 EFLOP/s at 4-bit

A local domain comprises 128 Jalapeño accelerators; a full production system is 2,048 accelerators, reaching 27 EFLOP/s total at 4-bit precision across the deployment.

Up to 104x better vs Nvidia GB200/GB300 at specific operating points

HotChips 2026 benchmarks (presented by Richard Ho, Ravi Narayanaswami, Chris Leary): 1.5–1.9x better performance per watt at peak throughput; 1.7–3.6x better latency; up to 104x better at operating points where Nvidia hardware struggles.

Homogeneous design — one chip for the entire inference pipeline

Unlike the industry trend of splitting workloads across specialized prefill, speculative-decode, and full-decode hardware, Jalapeño is a single balanced part designed for the entire inference workload — enabling simpler, homogeneous datacenter integration.

AI-assisted circuit optimization: <1% to ~90% roofline in 40 hours

Using OpenAI's own models during chip design, one attention kernel implementation went from under 1% of the memory/compute roofline to nearly 90% in roughly 40 hours — a concrete demonstration of LLM-accelerated silicon design at frontier speed.

13.4 PFLOPS 4-bit, 232 GB memory, 15.4 TB/s bandwidth

Full technical specs disclosed post-launch: Jalapeño delivers 13.4 petaflops of 4-bit compute, accesses 232 GB of advanced memory at 15.4 TB/s bandwidth.

3.6× lower latency vs. Nvidia GB300 at lower power draw

OpenAI benchmarks show Jalapeño reduces end-to-end prompt-to-last-token latency by up to 3.6× compared to the Nvidia GB300 it currently relies on, while also consuming less power.

Design team averaged under 100 engineers total

The Jalapeño team averaged fewer than 100 people across hardware, software, and supply chain roles throughout the project — excluding Broadcom's physical design staff.

OpenAI: system design; Broadcom: physical design from gates onward

OpenAI handled inference accelerator, memory hierarchy, and networking; Broadcom took over physical implementation from the gate level down — a clear division that enabled the rapid design timeline.

LLMs gave OpenAI engineers 'superpowers' for iteration speed

VP of Hardware Richard Ho: models let engineers 'explore a lot more paths' and 'do things a lot faster' without replacing human judgment. Experts note LLMs are particularly well-suited to chip design tasks 'in the linguistic domain.'

Team already pursuing second and third-generation chip designs

As of the full August 25, 2026 unveiling, OpenAI's ~100-person hardware team was actively working on successor Jalapeño generations, signaling a sustained custom silicon roadmap beyond the first chip.

Industry experts rate the design timeline 'likely best in class today'

UCSD professor Andrew Kahng called the speed 'likely best in class today.' Verkor.io co-founders noted Broadcom's involvement was essential to achieving the timeline, and said LLM improvements could yield even faster future cycles.